Low-Temperature Wet Conformal Nickel Silicide Deposition for Transistor Technology through an Organometallic Approach.

The race for performance of integrated circuits is nowadays facing a downscale limitation. To overpass this nanoscale limit, modern transistors with complex geometries have flourished, allowing higher performance and energy efficiency. Accompanying this breakthrough, challenges toward high-performance devices have emerged on each significant step, such as the inhomogeneous coverage issue and thermal-induced short circuit issue of metal silicide formation. In this respect, we developed a two-step organometallic approach for nickel silicide formation under near-ambient temperature. Transmission electron and atomic force microscopy show the formation of a homogeneous and conformal layer of NiSix on pristine silicon surface. Post-treatment decreases the carbon content to a level similar to what is found for the original wafer (∼6%). X-ray photoelectron spectroscopy also reveals an increasing ratio of Si content in the layer after annealing, which is shown to be NiSi2 according to X-ray absorption spectroscopy investigation on a Si nanoparticle model. I-V characteristic fitting reveals that this NiSi2 layer exhibits a competitive Schottky barrier height of 0.41 eV and series resistance of 8.5 Ω, thus opening an alternative low-temperature route for metal silicide formation on advanced devices.

Nanowire systems: technology and design.

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-all-around structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity and thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology.